Análise de Desempenho de um Roteador utilizando Diferentes Arquiteturas de Decremento em uma Rede-em-Chip

Authors

  • T. de Oliveira
  • N. Marranghello

DOI:

https://doi.org/10.5540/tema.2008.09.03.0427

Abstract

Uma rede-em-chip está sendo desenvolvida para permitir a implementação de uma Rede de Petri em hardware. Para determinar a melhor arquitetura do decrementador a ser incorporada ao roteador dessa rede foi desenvolvida uma abordagem baseada em equações matemáticas que computam as quantidades de portas lógicas e de níveis de lógica dos decrementadores e do roteador. Uma fórmula de desempenho foi estabelecida para realizar uma análise comparativa da arquitetura do roteador com cada um dos decrementadores.

References

[1] K.M. B¨uy¨uksahin, F.N. Najm, High-level area estimation, em “ISLPED ’02: Proceedings of the 2002 international symposium on Low power electronics and design”, pp. 271-274, New York, NY, USA, 2002.

J.P. Deschamps, G.J.A. Bioul, G.D. Sutter, “Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems”, Wiley-Interscience, New Jersey, 2006.

D.S. Gelosh, D.E. Steliff, Modeling layout tools to derive forward estimates of area and delay at the rtl level, ACM Trans. Des. Autom. Electron. Syst., 5, No. 3 (2000), 451-491.

G.D. Micheli, L. Benini, “Networks on Chips: Technology and Tools (Systems on Silicon)”, Morgan Kaufmann Publishers, San Francisco, 2006.

M. Nemani, F.N. Najm, High-level area and power estimation for vlsi circuits, em “ICCAD ’97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design”, pp. 114-119, Washington, DC, USA, 1997.

C. Ramachandran, F.J. Kurdahi, D.D. Gajski, A.C.-H. Wu, V. Chaiyakul, Accurate layout area and delay modeling for system level design, em “ICCAD ’92: Proceedings of the 1992 IEEE/ACM International Conference on Computeraided design”, pp. 355-361, Los Alamitos, CA, USA, 1992.

A. Srinivasan, G. Huber, D. LaPotin, Accurate area and delay estimation from rtl descriptions, IEEE Transactions on VLSI Systems, 6, No. 1 (1998), 168-172.

Downloads

Published

2008-06-01

How to Cite

de Oliveira, T., & Marranghello, N. (2008). Análise de Desempenho de um Roteador utilizando Diferentes Arquiteturas de Decremento em uma Rede-em-Chip. Trends in Computational and Applied Mathematics, 9(3), 427–436. https://doi.org/10.5540/tema.2008.09.03.0427

Issue

Vol. 9 No. 3 (2008)

Section

Original Article

License

Copyright

Authors of articles published in the journal Trends in Computational and Applied Mathematics retain the copyright of their work. The journal uses Creative Commons Attribution (CC-BY) in published articles. The authors grant the TCAM journal the right to first publish the article.

Intellectual Property and Terms of Use

The content of the articles is the exclusive responsibility of the authors. The journal uses Creative Commons Attribution (CC-BY) in published articles. This license allows published articles to be reused without permission for any purpose as long as the original work is correctly cited.

The journal encourages Authors to self-archive their accepted manuscripts, publishing them on personal blogs, institutional repositories, and social media, as long as the full citation is included in the journal's website version.